The present invention relates generally to semiconductor devices and more particularly to a semiconductor device having fuse state determination circuitry.
Semiconductor devices can use fuse structures than are programmable during the manufacturing process. One such application for a fuse structure is in a semiconductor memory device. In a semiconductor memory device, tight processing margins can cause defects to arise in a memory array. The semiconductor memory will be tested for defects and when there are defects, redundant memory cells can be used to replace defective bits of the memory array. The redundancy will typically be in the form of a redundant row or a redundant column of memory cells.
In order to program the redundant row or column to respond to the address value of a defective bit or bits, fuse structures will be programmed with the address value corresponding to the defective bit. In this case a fuse corresponding to one address bit will be left intact to create a short fuse condition for one address value and will be broken (blown) to create an open fuse condition for another address value. In this manner a redundant decoder can be programmed to respond to the address value corresponding to the defective memory cell or cells.
Referring now to FIG. 7, a circuit diagram of a conventional fuse circuit is set forth and given the general reference character 700. Conventional fuse circuit 700 has two fuses (F701 and F702) connected in series between a power supply voltage VCC and ground. Fuse F701 and fuse F702 are connected at a connecting point. Conventional fuse circuit 700 also has an inverter IV701 having an input connected to the connecting point of fuses (F701 and F702) and an output generating a logic value corresponding to the programmed configuration of fuses (F701 and F702).
When fuse F701 is broken, the input of inverter IV701 becomes a logic low thus generating a logic high output. When fuse F702 is broken, the input of inverter IV701 becomes a logic high thus generating a logic low output.
Conventional fuse circuit 700 requires two fuses (F701 and F702) for one programmable bit. Each fuse (F701 and F702) requires significant circuit area due to the accuracy and destructiveness of the fuse breaking (blowing) procedure. Thus, conventional fuse circuit 700 consumes significant chip area, which increases manufacturing costs. Furthermore, there are typically many fuse circuits on a chip.
Also, conventional fuse circuit 700 consumes significant amounts of current before a fuse (F701 or F702) is broken. This is undesirable because the increased current consumption can cause the chip to operate differently in the test condition than it would in a normal operating condition. This can create testing integrity problems.
Another drawback with conventional fuse circuit 700 is that a fuse (F701 and F702) must be broken for each conventional fuse circuit 700 on the chip regardless as to whether there are any defects. Otherwise, operating current would be undesirably high.
In order to address some of the above-mentioned problems, other fuse circuit configurations have been developed.
Referring now to FIG. 8, a conventional fuse evaluation circuit including fuses is set forth in a schematic diagram and given the general reference character 800.
Conventional fuse evaluation circuit 800 has a reference voltage generation circuit 810 and a fuse circuit 820.
Fuse circuit 820 has a single fuse F801 and transistor T801. Fuse F801 is connected between a power supply VCC and a connecting node N801. Transistor T801 has a source/drain path connected between ground and connecting node N801. A control gate of transistor T801 receives a reference voltage VG8 from reference voltage generation circuit 810. Fuse circuit 820 also has a latch circuit L822 connected to connecting node N801.
Reference voltage generation circuit 810 has an inverter IV810 connected to receive a fuse evaluation signal S801 and has an output connected to control gates of p-channel transistor MP801 and n-channel transistor MN802. Reference voltage generation circuit 810 has a constant-current source 1801 connected between a power supply VCC and the source of p-channel transistor MP801. P-channel transistor has a drain connected to reference voltage VG8. Reference voltage generation circuit 810 also has a n-channel transistor MN801 having a drain and a gate connected to reference voltage VG8 and a source connected to ground. N-channel transistor MN802 has a drain connected to reference voltage VG8 and a source connected to ground.
Reference voltage generation circuit 810 receives a fuse evaluation signal S801 and generates a reference voltage VG8. Fuse circuit 820 receives the reference voltage and evaluates the condition of fuse F801.
When fuse evaluation signal S801 is logic low, the output of inverter IV810 becomes high, thus p-channel transistor MP801 is turned off and n-channel transistor MN802 is turned on. Thus, reference voltage generation circuit 810 provides a reference voltage VG8 that is at ground. This turns off transistor T801, which reduces the standby current consumption in fuse circuit 820.
When the status of fuse F801 is to be evaluated, evaluation signal S801 transitions from logic low to logic high. Inverter IV810 provides logic low to the control gates of p-channel transistor MP801 and n-channel transistor MN802. Thus, p-channel transistor MP801 is turned on and n-channel transistor MN802 is turned off. This allows constant current source 1801 to provide a current through p-channel transistor and n-channel transistor MN801 to ground. N-channel transistor MN801 is configured in a diode configuration to provide a reference voltage VG8 to the control gate of transistor T801 in fuse circuit 820. In this manner, transistor T801 is turned on and the level of reference voltage VG8 and size of transistor T801 is chosen so that transistor T801 provides an on-impedance path that has a resistance that is approximately two times larger than the intact resistance of fuse F801. Latch circuit L801 includes an inverter to receive the voltage at connecting node N801. The threshold of the inverter is VCC/2. Thus, if the potential of connecting node N801 is less than VCC/2, fuse F801 is evaluated as broken and a low logic level is latched in latch circuit L822. If the potential of connecting node N801 is greater than VCC/2, fuse F801 is evaluated as intact and a high logic level is latched in latch circuit L822. The potential of connecting node N801 is determined by the ratio of the on-resistance of transistor T801 and the resistance of intact or broken fuse F801.
However, a fuse such as fuse F801 is typically blown by a laser and is not always completely broken. A fuse F801 is sometimes only partially broken which can cause the fuse F801 to have a resistance in the range of several tens of kxcexa9. In a case in which conventional fuse evaluation circuit 800 is used, the resistance of a partially broken fuse can cause the potential of connecting node N801 to be very close to VCC/2 during the fuse evaluation. This can create cases where fuse F801 may be evaluated to be broken under a certain operating condition, but with a variation in temperature or voltage, the on-resistance of transistor T801 may vary enough to allow the fuse F801 to be evaluated as intact and vice-versa. Furthermore, when a fuse F801 is partially broken, the resistance may change over time allowing inconsistent evaluations.
Semiconductor devices must be screened during the manufacturing stage to ensure that only passing units are sold to the customer. However, if there are fuse evaluations that indicate a passing condition during testing only to fail at a later time, then the screening process has been inadequate. Thus, it is necessary to properly evaluate partially broken fuses that may pass under some conditions but can create failures in the future. Using conventional evaluation circuit 800, such semiconductor devices are not properly screened.
One approach to addressing the screening of partially broken fuses is disclosed in Japanese Laid-Open Patent Publication No. 10-62477. This approach will now be explained with reference to FIG. 9.
Referring now to FIG. 9, a conventional fuse evaluation circuit is set forth in a circuit schematic diagram and given the general reference character 900.
Conventional fuse evaluation circuit 900 has a resistor 912 connected between a power supply VDD and a connection node N901 and a fuse F901 connected between connection node N901 and ground. An inverter IV910 is connected to receive connecting point N901 as an input. Conventional fuse evaluation circuit 900 also has an n-channel transistor having a drain connected to connection node N901, a source connected to a resistor 918 and a gate connected to a test mode signal TEST901. Resistor 918 is connected between ground and the source of n-channel transistor MN901.
In a normal operation of conventional fuse evaluation circuit 900, test mode signal TEST901 is at a logic low, thus n-channel transistor MN901 is turned off. In this mode, the status of the fuse is determined by the ratio of the resistance of fuse F901 and resistor 912. However, in the fuse evaluation test mode, test mode signal TEST901 is at a logic high. N-channel transistor MN901 is turned on. This lowers the potential of connecting point N901. In this manner, fuse F901 can be determined to be intact even if it is partially broken. Such a determination would cause the device to fail and become rejected.
However, in the conventional fuse evaluation circuit 900, resistors 912 and 918 require relatively large resistance values. This can cause the size of the conventional fuse evaluation circuit 900 to become large, particularly if resistors 912 and 918 are formed from a metal layer. If resistors 912 and 918 are formed from a layer such as polysilicon, they can become prone to process variations in manufacturing. Also, because of the relatively large resistance values, connecting point N901 does not settle quickly to its quiescent condition when the fuse evaluation test mode is entered causing an increase in time necessary to properly evaluate the condition of fuse F901.
Also, because there are typically a large number of fuses requiring such a conventional fuse evaluation circuit 900 on a semiconductor memory device such as a dynamic random access memory (DRAM), and other memory devices, the chip area can become large. This increases manufacturing costs because fewer devices can be built on a single wafer.
Also, in order to assure that devices are screened so that they will properly operate under all specified conditions, a relatively high precision can be needed to properly calibrate elements (resistors 912, resistor 918, and n-channel transistor MN901) in conventional fuse evaluation circuit 900. It can be difficult to retain a high relative precision between these devices because they are manufactured in different processing steps.
In view of the above discussion, it would be desirable to provide a semiconductor device having a fuse evaluation circuit that can provide sufficient evaluation margins to properly screen unreliable fuse conditions. It would also be desirable to provide a fuse evaluation circuit that enables a fast fuse condition determination. It would also be desirable to provide a fuse evaluation circuit having a reduced size. It would also be desirable to provide a fuse evaluation circuit having a relatively high precision so that it can properly be determined if a partially broken condition exists.
According to the present embodiments, a semiconductor device having a fuse evaluation circuit is provided. The fuse evaluation circuit can include a reference voltage generation circuit, a fuse circuit and a fuse evaluation control circuit.
According to one aspect of the embodiments, the fuse circuit can include a fuse arranged in series with an evaluation transistor and providing an evaluation potential. The evaluation transistor may have a controllable impedance path.
According to another aspect of the embodiments, a fuse evaluation control circuit can vary the impedance of an evaluation transistor in accordance with different modes of operation.
According to another aspect of the embodiments, reference voltage generation circuit can provide a reference voltage for setting the impedance of evaluation transistor. Fuse evaluation control circuit can vary the impedance of evaluation transistor by varying the reference voltage in accordance with different fuse evaluation modes of operation.
According to another aspect of the embodiments, fuse evaluation control circuit can include a first evaluation control circuit for decreasing the reference voltage and a second evaluation control circuit for increasing the reference voltage.
According to another aspect of the embodiments, first evaluation control circuit can reduce an impedance path from the reference voltage to a low power supply.
According to another aspect of the embodiments, the first evaluation control circuit can include a transistor having a gate and drain coupled to the reference voltage and a source coupled to the drain of a second transistor. The second transistor can have a source coupled to a low power supply and a control gate coupled to receive an evaluation mode control signal.
According to another aspect of the embodiments, the first evaluation control circuit can include a plurality of impedance paths arranged in parallel. Each impedance path comprising a transistor having a gate and drain coupled to the reference voltage and a source coupled to the drain of a second transistor. The second transistor can have a source coupled to a low power supply and a control gate coupled to receive an evaluation mode control signal.
According to another aspect of the embodiments, second evaluation control circuit can reduce an impedance path from the reference voltage to a current source coupled to a high power supply.
According to another aspect of the embodiments, the second evaluation control circuit can include a transistor having a source coupled to a current source, a drain coupled to the reference voltage and a gate coupled to receive an evaluation mode control signal.
According to another aspect of the embodiments, the first evaluation control circuit an include a plurality of impedance paths arranged in parallel. Each impedance path comprising a transistor having a source coupled to a current source, a drain coupled to the reference voltage and a gate coupled to receive an evaluation mode control signal.
According to another aspect of the embodiments, a test margin can be set by selectively enabling controllable impedance paths arranged in parallel to provide the reference voltage.
According to another aspect of the embodiments, the evaluation transistor may be an n-channel IGFET.
According to another aspect of the embodiments, fuse circuit can include a latch circuit coupled to evaluation node. The latch circuit can provide a latched fuse determination signal having a logic level determined by the potential of the fuse evaluation node.
According to another aspect of the embodiments, a fuse evaluation circuit can be enabled during a fuse evaluation timing. A fuse evaluation control circuit can also be enabled during the fuse evaluation timing.
According to another aspect of the embodiments, a fuse evaluation circuit can have a first mode of operation evaluating a fuse in a first state or a second state in accordance with whether the fuse has a resistance greater than or less than a first value.
According to another aspect of the embodiments, the fuse evaluation circuit can have a second mode of operation evaluating the fuse in the first state or the second state in accordance with whether the fuse has a resistance greater or less than a second value. The second value can be greater than the first value.
According to another aspect of the embodiments, the fuse evaluation circuit can have a third mode of operation evaluating the fuse in the first state or the second state in accordance with whether the fuse has a resistance greater or less than a third value. The third value can be less than the first value.